The present invention relates to a test pattern generating apparatus which generates galloping, walking and various other test patterns for testing semiconductor memories.
Conventional semiconductor memory test pattern generating apparatuses have such a construction as proposed, for example, in U.S. patent application Ser. No. 26,246 now U.S. Pat. No. 4,293,950, (filed Apr. 2, 1979) entitled "Test Pattern Generating Apparatus." In such a prior art example, an instruction memory is read out by an address from an address counter and an address generating instruction in the output read out from the instruction memory is decoded and executed by an address generator to generate an address pattern. A data generating instruction in the read output is decoded and executed by a data generator to generate a data pattern. A memory under test is accessed by the address pattern to read it out or to write therein the data pattern. Status information from the address generator and the data generator, such as the address pattern and the data pattern therefrom, and a conditional branch instruction in the output read out from the instruction memory are provided to a control circuit. By a control signal from the control circuit, the address counter is controlled to step or set its content to a jump address in the output read out from the instruction memory.
With such a conventional test pattern generating apparatus, since the time for obtaining the abovesaid control signal is included in the operation period from the execution of an instruction to the execution of the next instruction, it is difficult to generate test patterns at high speed. If the test is conducted at high speed, when the abovesaid jump takes place, there occurs what is called a dummy cycle in which no test pattern is applied to the memory under test. An appreciable number of test patterns repeat the same sequence from a certain address to another address of the memory under test, such as galloping, walking and like patterns. In the case of repeating the same sequence, the address counter of the instruction memory is usually jump-controlled, so that in the high-speed test, the dummy cycle often occurs, resulting in the test becoming undesirably lengthy.